1. Field of the Invention
The present invention relates to a semiconductor device having a compensation capacitor, and particularly relates to a semiconductor device in which a basic end cell provided with the compensation capacitor is arranged adjacent to an end of a circuit cell, and to an arrangement method of the compensation capacitor.
2. Description of Related Art
In recent years, as increases in both scale and speed have been required for semiconductor devices, supply voltages thereof have become lower. Therefore, operating margin of a supply voltage against noise tends to decrease, and thus measures for stabilizing the supply voltage supplied to internal circuits of a semiconductor device have been required. A structure has been conventionally proposed in which compensation capacitors are arranged in a semiconductor device and are connected to a supply voltage line in order to suppress fluctuation of the supply voltage line (for example, refer to Patent Reference 1). For example, with reference to FIG. 3 of the Patent Reference 1, compensation capacitors 30 to 34 are arranged in empty regions at both ends in a longitudinal direction of the figure in a circuit cell and are capable of being connected to a desired supply voltage line through contacts. By this structure, capacitance values of the compensation capacitors can be obtained corresponding to the empty regions in the circuit cell, thereby suppressing the fluctuation of the supply voltage and stabilizing the operation of the semiconductor device.    Patent Reference 1: Japanese Patent Application Laid-open No. 2006-253393
However, even if the structure of the Patent Reference 1 is employed, the arrangement of the compensation capacitors is restricted by the empty regions in the circuit cell, and thus it may be often difficult to obtain compensation capacitors capable of reliably and sufficiently suppressing the fluctuation of the Meanwhile, since automatic cell design has come to be used in recent semiconductor devices for the purpose of drastically reducing the time required for cell design, the arrangement of the compensation capacitors is required to fit the automatic cell design.
FIG. 13 shows an example of the automatic cell design in a semiconductor device. In FIG. 13, a circuit cell 100 of the semiconductor device is formed by aligning a plurality of elements 101 (e.g., inverters, NAND gates and NOR gates), which are preliminarily formed as components of a logic circuit achieving a predetermined function, in a lateral direction of FIG. 13 based on circuit information. Each of the elements 101 includes, for example, diffusion layers 102, gate lines 103, lines 104 of a metal layer M1, and lines 105 of a metal layer M2. Further, there are provided contacts V1 connecting between the diffusion layers 102 and the metal layer M1, contacts V2 connecting between the metal layers M1 and M2, and contacts VG connecting between the metal layer M1 and the gate lines 103.
Here, in the following description, “circuit cell” means a cell formed using one or more elements such as inverters, NAND gates and NOR gates. Accordingly, “circuit cell” can be formed using one element, and can be formed using a combination of a plurality of elements.
Upper and lower parts of FIG. 13 are a P-channel region and an N-channel region respectively, and a region therebetween is an inter-element connection region R1. In the automatic cell design, circuit connection is completed by connecting predetermined lines 104 to each other using connecting lines 106 of the metal layer M2 in the inter-element connection region R1 based on the circuit information. Therefore, the inter-element connection region R1 needs to have a size capable of arranging a plurality of connecting lines 106 in parallel. Although lines of the metal layers M1 and M2 are arranged in the inter-element connection region R1 shown in FIG. 13, there is a region therebelow where the diffusion layers 102 and the gate lines 103 are not arranged. If the circuit connection of the circuit cell 100 becomes complicated, an area of the inter-element connection region R1 is enlarged, and utilizing this area effectively has been a problem to be solved.